1. Field of the Invention
The present invention relates to a level shift circuit.
2. Description of the Related Art
FIG. 3 is a circuit diagram for illustrating a related-art level shift circuit 300.
The related-art level shift circuit 300 includes a high level power supply terminal 301, an output terminal 302, a ground terminal 303, a floating power supply 304, a low level power supply 305, a PWM terminal 306, a pulse generating circuit 311, resistors 316 and 317, high withstand voltage NMOS transistors 314, 315, 323, and 324, a logic circuit 310 including inverter circuits 318 and 319 and an RS flip-flop circuit 320, driver circuits 321 and 322, and a low-side drive signal input terminal 307.
Connection in the related-art level shift circuit 300 is described with reference to FIG. 3.
The pulse generating circuit 311 has an input connected to the PWM terminal 306. The high withstand voltage NMOS transistor 314 has a gate connected to a first output of the pulse generating circuit 311, a source connected to the ground terminal 303, and a drain connected to one end of the resistor 316 and an input of the inverter circuit 318. The high withstand voltage NMOS transistor 315 has a gate connected to a second output of the pulse generating circuit 311, a source connected to the ground terminal 303, and a drain connected to one end of the resistor 317 and an input of the inverter circuit 319.
The RS flip-flop circuit 320 has a set terminal S connected to an output of the inverter circuit 318, a reset terminal R connected to an output of the inverter circuit 319, and an output terminal Q connected to an input of the driver circuit 321.
The driver circuit 321 has an output connected to a gate of the high withstand voltage NMOS transistor 323. The high withstand voltage NMOS transistor 323 has a source connected to the output terminal 302, and a drain connected to the high level power supply terminal 301.
The floating power supply 304 has one end connected to the other end of the resistor 316, the other end of the resistor 317, and a power supply input of the driver circuit 321, and the other end connected to the output terminal 302 and a low level power supply input of the driver circuit 321. The driver circuit 322 has an input connected to the low-side drive signal input terminal 307, a power supply input connected to one end of the low level power supply 305, and a low level power supply input connected to the ground terminal 303. The high withstand voltage NMOS transistor 324 has a gate connected to an output of the driver circuit 322, a source connected to the ground terminal 303, and a drain connected to the output terminal 302. The low level power supply 305 has the other end connected to the ground terminal 303.
Operation of the related-art level shift circuit 300 is described.
First, how the related-art level shift circuit 300 operates when a rising edge appears in a PWM signal is described. Here, the PWM signal is a signal having an amplitude equal to that of the voltage of the low level power supply 305.
The pulse generating circuit 311 receives a PWM signal, and outputs, at timing of the rising edge of the PWM signal, a one-shot pulse to the gate of the high withstand voltage NMOS transistor 314 as a first output signal S1. The high withstand voltage NMOS transistor 314 converts the one-shot pulse being the signal S1 into a current, and supplies the current to the resistor 316. In this way, a voltage HV1 is generated at the one end of the resistor 316.
The inverter circuit 318 supplies an inverted signal S2 of the voltage HV1 to the set terminal S of the RS flip-flop circuit 320. The RS flip-flop circuit 320 is set through this operation, and outputs a HIGH level from the output terminal Q as an output signal Q0. The logic circuit 310 operates with the floating power supply 304 as illustrated in FIG. 3.
The driver circuit 321 buffers the signal Q0 being the HIGH level input thereto, and drives the high withstand voltage NMOS transistor 323 by an output signal DRV. As a result, the high withstand voltage NMOS transistor 323 is turned on, and an output voltage OUT at the output terminal 302 rises. The low-side drive signal input terminal 307, to which a signal for alternately turning on and off the high withstand voltage NMOS transistors 323 and 324 is input, receives a LOW level in this case where the signal Q0 is the HIGH level. That is, the high withstand voltage NMOS transistor 324 is turned off.
Next, how the related-art level shift circuit 300 operates when a falling edge appears in a PWM signal is described, subsequently to the above-mentioned operation.
The pulse generating circuit 311 receives a PWM signal, and outputs, at timing of the falling edge of the PWM signal, a one-shot pulse to the gate of the high withstand voltage NMOS transistor 315 as a second output signal R1. The high withstand voltage NMOS transistor 315 converts the one-shot pulse being the signal R1 into a current, and supplies the current to the resistor 317. In this way, a voltage HV2 is generated at the one end of the resistor 317.
The inverter circuit 319 outputs an inverted signal R2 of the voltage HV2 to the reset terminal R of the RS flip-flop circuit 320. The RS flip-flop circuit 320 is reset through this operation, and outputs the LOW level from the output terminal Q as the output signal Q0.
The driver circuit 321 buffers the LOW level input thereto, and turns off the high withstand voltage NMOS transistor 323. The HIGH level is input to the low-side drive signal input terminal 307 after the high withstand voltage NMOS transistor 323 is turned off. That is, the high withstand voltage NMOS transistor 324 is turned on after the high withstand voltage NMOS transistor 323 is turned off As a result of this operation, the output voltage OUT at the output terminal 302 drops.
In this manner, a PWM signal having an amplitude equal to that of the voltage of the low level power supply 305 is converted (level shifted) into a signal having an amplitude equal to that of the voltage of the floating power supply 304, and is then output from the output terminal Q of the logic circuit 310 as the output signal Q0.
The high withstand voltage NMOS transistor 323 is driven by the output signal Q0, and as a result, the output voltage OUT having an amplitude between those at the high level power supply terminal 301 and the ground terminal 303 is obtained.
A level shift circuit having a configuration similar to that of the level shift circuit 300 is described in Japanese Patent Application Laid-open No. 2011-109843, for example.
FIG. 4 is an illustration of voltage waveforms corresponding to voltages at respective nodes of the related-art level shift circuit 300.
As illustrated in FIG. 4, the PWM signal shifts from the LOW level to the HIGH level at time t0, and the output voltage OUT rises from time t0 to time t1. It can been seen that in a period T in which the output voltage OUT rises, rise of the output voltage OUT propagates as described above, and a spike noise N is generated in each of the first and second output signals S1 and R1 of the pulse generating circuit 311, resulting in voltage fluctuation. In particular, addition of the noise N to the one-shot pulse being the output signal S1 leads to a fear that a voltage higher than the highest voltage of the one-shot pulse propagates to the pulse generating circuit 311.